Wednesday, 2 September 2015

Design of A Low Power and High Speed Integrated Circuit using Modified Feed Through Logic

Design of A Low Power and High Speed Integrated Circuit using Modified Feed Through Logic
Shazia Rana Begum1, Md.Qaiser Reza2
M.Tech in Electronics & Communication Engineering(VLSI-Design)
Department of Electronics & Communication Engineering
Al-Falah School of Engineering & Technology, Faridabad, Haryana, INDIA.

Abstract A modified approach for Feed-Through logic (FTL) is developed in this paper to provide a design of a low power and high performance dynamic circuit . The need for faster circuits with low power dissipation has made it common practice to use feedthrogh logic. The proposed circuit for low power improves dynamic power consumption as compared to the existing feedthrough logic and to further improve its speed we proposed another circuit which improves the speed by sacrificing dynamic power consumption. The proposed circuit is simulated using 180 nm, 1.8 V CMOS process technology.FTL performs a partial evaluation in a computational block before its input signals reach a valid level, and performs a quick final evaluation as soon as the inputs arrive, leading to a reduction in the delay.  Intensive simulation results in Cadence environment shows that the proposed modified low-power structure reduces the dynamic power approximately by 35% and the modified structure for high performance achieves a speed up- 1.3 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing feedthrough logic. The concept is validated through extensive simulation.Problems associated with domino logic like limitation of non-inverting only logic  and the need of output inverter are eliminated.
Keywords Feedthrough logic (FTL);dynamic CMOS logic circuit; high performance; low-power adder.

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