Abstract— A digital low-dropout regulator (D-LDO) with reduced transient response time and overshoot/undershoot is proposed. The reduction of response time is achieved by using transient response boost technique. The loop gain is increased at the time of deviations exceeding the limit and the loop gain is returned after the output voltage is settled. On comparing LDO with and without transient response boost technique the settling time is reduced. The regulation is done in time mode with the help of high linear voltage to time convertor (VTC) and time to digital convertor. The time domain analog to digital conversion achieves high resolution at low power and small area. And multibit cyclic TDC for high level current efficiency is used.
Key words—Current efficiency, cyclic TDC, digital low-dropout regulator (D-LDO), transient-response boost mode (TRBM), voltage-to-time converter (VTC).
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